Industry Expert Blogs

Verifying complex SoCs takes a lot of effort. Our user surveys show that around 70% of the engineering resource involved in taping out a complex SoC is spent on verification, with half of that time consumed by debug.

Without a well-thought-out verification environment, verification teams waste a huge amount of time recreating verification environments at the SoC level to enable chip-level verification because they don’t consider reuse of the environments they originally developed to verify their block-level IP. Even across the same abstraction level, the inability to reuse the same verification IP and environment to support both simulation and emulation causes delays and consumes more engineering resources than necessary.

Being able to consistently reuse verification environments across an entire SoC project boosts verification productivity significantly. However, to gain from these productivity benefits requires verification teams to carefully plan their approach for all stages of the verification process.

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