English
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Industry Expert Blogs
|
Expectations of a Verification IP User: Transaction ModelingVIP Experts Blog - SynopsysJan. 21, 2015 |
In my blog posts, I will be sharing my expectations from a Verification IP. I will begin with Transaction Modeling.
Having played a role in both developing as well as in using Verification IPs, I consider the transaction class to be the most important component of a VIP. The quality of a transaction class defines the quality of the VIP. Be it UVM, or any other methodology, deciding on the transaction class structure requires sufficient planning as it affects the overall VIP architecture and the verification environment.
Let me list down some of the guidelines which I think are relevant:
Related Blogs
- Expectations of a Verification IP user: Transaction modeling
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- ARM vs RISC-V: Beginning of a new era
- The Arm Ecosystem: More than Just an Ecosystem, it's Oxygen for SoC Design Teams