Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
Cadence Firmware Packages Enable Successful IP IntegrationCadence IP Blog - Cyprian WronkaJan. 27, 2015 |
Building a system on chip (SoC) from IP blocks requires system-level integration and bring-up, and that requires firmware working on the target. In a fast-paced development cycle, it is crucial to provide customers with IP blocks and tested firmware. In particular, at the bring-up stage, there may be very few debug capabilities at hand and, therefore, a firmware package that is pre-tested on multiple platforms and systems will speed up the integration effort. The driver package provides the following benefits:
- Abstracts implementation details through well-defined and use case-driven application programming interface (API)
- Enables early (pre-silicon) development of a board support package (BSP) / software development toolkit (SDK)
- Provides early reference to silicon validation.
Cadence soft-IP cores now come with firmware that has been tested in simulation, on our emulation platform and on FPGA boards.
Related Blogs
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions
- Arm and Arteris Drive Innovation in Automotive SoCs
- Obsolete & EOL Parts
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Enhanced ARM DesignStart eliminates upfront license fees for ARM Cortex-M0 and Cortex-M3 processors