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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
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IP Requirements for Verifying CHI-Based DesignsCadence IP Blog - Dimitry Pavlovsky, CadenceMar. 05, 2015 |
Just as IP components offload design effort, verification IP (VIP) components offload verification effort. VIP components are used to monitor traffic and substitute for selected master and slave components to enable controlled stimulus generation and coverage collection within an SoC design. To be effective in verifying CHI-based designs, the VIP must deliver three major capabilities. They are:
- Stimulus generation: Mimicking all possible scenarios to cover the full verification space
- Coherency checking: Ensuring coherency and system compliance with the CHI specification
- Coverage: Measuring functional coverage and ensuring verification completeness
