Industry Expert Blogs

In keeping with 50 years of Moore’s Law, this post is about the results we have obtained for 7-nm FinFET’s and 5-nm nano-wire standard cell logic libraries. These transistors are very new. Trade-offs are being made by Synopsys’ device physicists in terms of electrostatics, leakage, patterning, manufacturability and transistor performance. Before I go any further I should explain that although I work in our IP team, I get to see the exciting work our TCAD (technology computer aided design) team does in developing the fundamental devices used in the IP like standard cells, USB, SERDES and DDR.

What’s even more exciting is that their work on quantum effects at these nodes impacts the FinFET or nano-wire device design – fin width, fin height, different materials (for spacers, channels etc.) – generally anything that can impact the bandgap. Once the transistor or nano-wire properties are defined, a standard cell library can be prepared to see power:performance trade-off in terms of energy versus delay. This feedback can then be applied back to the device engineers.

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