English
Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
|
EDPS 2015: Have We Hit the Power Floor?The Fuller View Blog - Brian FullerMay. 04, 2015 |
When it comes to pushing power as low as it can go, the answer is part technological, part cultural.
That was the conclusion of a panel of experts at the annual Electronic Design Processes Symposium in Monterey April 24.
The panel, moderated by Cadence blogger Richard Goering (pictured far left), was titled, “Can Power Go Any Lower, Or Have We Amost Hit the Floor, Especially for IoT Devices?” And experts from UC San Diego, Atrenta, Cadence, eSilicon, FinSix, and Synopsys wrestled with the question for nearly an hour by the Pacific Ocean.
And their consensus for how the industry designs ultra-low power devices and systems in the coming years was surprising in its breadth.
Related Blogs
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets
- Experts Talk: RISC-V CEO Calista Redmond and Maven Silicon CEO Sivakumar P R on RISC-V Open Era of Computing
- Decipher the Meaning of Silicon-as-a-Service
- Why, How and What of Custom SoCs