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Dynamic Power Estimation Hits Limits of SoC DesignsEETimes Blog - Lauro Rizzatti, Verification ConsultantMay. 11, 2015 |
The unstoppable rise in design sizes has been taxing heavily the EDA verification tools. Dynamic power estimation tools are one example.
Several incentives entice consumers to upgrade their mobile gadgets frequently. From more functionality and enhanced user experience, to a more attractive user interface to enliven usage, lighter weight, longer battery life, and the list does not stop here. All considered, it seems that long battery life tops the list, and longer battery life directly correlates to lower power consumption.
Power consumption in microelectronics has seen a constant drop since the invention of the planar integrated circuit by Noyce and Kilby five decades ago. The planar technology made it possible to scale (shrink) solid-state devices. The smaller the transistors, the more transistors in the same area, the faster they switch, the less energy they consume and the cooler the chips run (for the same number of transistors).
