English
400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
Industry Expert Blogs
|
I Don't Know Much About Aart...SemiWiki - Paul McLellanJun. 15, 2015 |
Actually, like anyone who has been in EDA for more than a decade or two (or three) I know quite a bit about Aart. But I still learned quite a bit about his views at the Fireside Chat at DAC where Ed Sperling talked to Aart for three-quarters of an hour.
Aart has a great talent at taking various small trends in the industry and aggregating them up to a significant trend. Or looking at some aspect of the industry and generalizing it in an interesting way. I won't try and cover everything (it took Aart 45 minutes to say it and it would take you 45 minutes to read it...not to mention my note-taking skills are not that good.)
Related Blogs
- Let's Talk PVT Monitoring: Understanding Your Chip's Age
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions
- Obsolete & EOL Parts
- Experts Talk: RISC-V CEO Calista Redmond and Maven Silicon CEO Sivakumar P R on RISC-V Open Era of Computing