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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Industry Expert Blogs
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Intel -- The Litmus TestEETimes Blog - Zvi Or-Bach, Founder, MonolithIC 3D IncJun. 24, 2015 |
How will we bridge the gap between widely different estimates for transistor cost to scale to upcoming nodes? Whom are we to believe?
Vivek Singh, an Intel fellow, in his DAC 2015 keynote Moore's Law at 50: No End in Sight presented again the Intel chart below suggesting straight (log) line transistor cost reduction with dimensional scaling. In fact, his cost/transistor drop even seems to accelerate beyond the linear at 14 and 10 nanometers.
