English
55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Industry Expert Blogs
|
Arteris tackles tyranny of wiresMannerisms - David MannersOct. 27, 2015 |
Wires are the problem. The smaller they get the more resistance they have and the closer together they are the more they interfere with eachothers’ signals and the more transistors on the chip the more wires there have to be.
But the whole direction of scaling is to create more wires, thinner wires and wires which are closer together.
Related Blogs
- Moortec "Let's Talk PVT Monitoring" Series with CTO Oliver King
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Digitizing Data Using Optical Character Recognition (OCR)
- The design of the NoC is key to the success of large, high-performance compute SoCs
- Semiconductor Design Firms are Embracing the Public Cloud. Here are 5 Reasons Why.