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In 2013, Tensilica (subsequently acquired by Cadence) released its second-generation image processing IP core, the IVP, which also supported modest computer vision capabilities (Figure 1). One year later came the IVP-EP, which supported increased data precision flexibility, boosting overall performance in many applications and therefore further expanding the core's vision processing function reach. And in October of this year, Cadence further extended the product line, unveiling its latest Tensilica Vision P5 DSP.

The Vision P5's memory interface represents one of the more notable architecture upgrades compared to its predecessors. While its 1,024-bit bus width is unchanged, its effective bandwidth is significantly increased, according to product line director Dennis Crespo.

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