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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Industry Expert Blogs
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DDR/LPDDR 4/3 Combo PHY in TSMC 28HPC Silicon Proven at 2400 MbpsCadence IP Blog - Jacek DudaMar. 21, 2016 |
Back in October we announced the TSMC 28HPC tapeout of our DDR/LPDDR 4/3 Combo PHY. Since then we have made great progress with customers, and our own silicon bring up. Most recently, the combo PHY IP is brought up in our lab and running at 2400 Mbps.
Many price sensitive consumer products continue to leverage 28nm technology for affordable high performance and low power consumption. Originally announced at Memcon 2014, and developed for TSMC 16FF+, this IP has been selected by multiple customers for their mobile and enterprise server/networking applications. Read about how that IP has been demonstrated running at 3200Mbps here.
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