Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
IP Group @ 53rd DAC - Veni Vidi ViciCadence IP Blog - Jacek DudaJun. 20, 2016 |
Another DAC, and this year someone put a jalapeno in my margarita at the Denali Party. The burn came on slow, and was merciless. So we all yelled “Carpe Diem!”
The really good news is that there was a lot of traffic at the floor show, and we seemed to garner the largest crowds. Overall attendance was strong. And we saw increased interest in customers talking with our IP technical experts at the Expert Bar. We shared concepts for selecting the right DDR IP (Figure 1), protocol-level debugging (Figure 2), transaction-level SoC performance analysis (Figure 3), next-generation datacenter equipment architecture (Figure 4), and also discussed an IoT device and system rapid prototyping solution (Figure 5).
There are interesting dynamics in the supply of DDR/LPPDR memory chips. And different designs have difference technical requirements, and economics that would impact whether selecting DDR or LPDDR would be best, and which version. Figure 1 supplied the technical background for discussing these points.