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Hybrid Memory Cube (HMC) is a memory architecture that was developed by Micron in 2011. It was developed in response to the high-bandwidth, high-efficiency memory requirements of multi-core processing in supercomputing and advanced network systems. HMC represents a fundamental and key change in how memory is used in the system. By placing intelligent memory on the same substrate as the processing unit, each part of the system can do what it's designed to do far more optimally than any previous technology.

Every HMC memory chip has a small, high-speed logic layer that sits below vertical stacks of DRAM die that are connected using through-silicon-via (TSV) interconnects. The DRAM has been designed to handle data exclusively, with the logic layer handling all DRAM control within the HMC. The energy-optimized DRAM array provides efficient access to memory bits via the logic layer, providing an intelligent memory device truly optimized for performance and energy efficiencies.

- See more at: https://community.cadence.com/cadence_blogs_8/b/ip/archive/2016/07/18/what-s-new-with-hybrid-memory-cube-hmc#sthash.2K3lzdP3.dpuf

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