MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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PCI Express Trends and News at PCI-SIG 2016Cadence IP Blog - Steven Brown, CadenceJul. 19, 2016 |
PCI-SIG Developers Conference 2016 is now history, taking place at the Santa Clara Convention Center at 28th-29th June, once again proving it’s not an event you want to miss. With PCIe 4.0 standard maturing, we’re seeing a lot of action in the market, though there are questions that have to be answered.
There were questions about PCIe 5.0, and though it will become an important project, the SIG wisely is staying focused on finishing PCIe 4.0. From the PR session we know PCIe 5.0 will be 32 GT/s, with specifications appearing in 2017.