Aeonic Generate Digital PLL for multi-instance, core logic clocking
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RISC-V Available in SiliconBreakfast Bytes - Paul McLellanDec. 12, 2016 |
One of the announcements at the recent RISC-V workshop was by SiFive. This is the company started by the creators of the RISC-V instruction set architecture (Krste, Andrew, and Yunsup) to commercialize silicon implementations.
Four months ago, at the previous RISC-V workshop, they announced FPGA implementations of the two flavors, Freedom Everywhere (32-bit microcontroller) and Freedom Unleashed (64-bit multi-core, high performance). They also announced that silicon would be coming "soon."
Well, it is now "soon."