Industry Expert Blogs

The JESD204B specification is the newer version published by JEDEC standard for data converters and logic devices. If you are working on high-speed data capture designs using an FPGA, you’ve would have heard the new buzz word, ‘JESD204B’. This newer version provides significant benefits over LVDS and CMOS interfaces, as it includes an easier layout and reduced pin-count. The JESD204B standard has a layered architecture, and is comprised of 3 layers beginning with Transport Layer at top, extending to Link Layer in middle and Physical layer at the bottom. Mirror Image is the structure at receiver side, with bottom up approach (Physical layer -> Link layer -> Transport layer). Each layer has a unique function to perform.

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