Industry Expert Blogs
Rambus showcases 56G Multi-Protocol SerDes (MPS) PHY at the Samsung Foundry ForumRambus BlogMay. 24, 2017 |
Rambus is attending the Samsung Foundry Forum at the Santa Clara Marriott on May 24th. The company will be showcasing its 56G SerDes PHY, which is being developed on Samsung’s 10nm LPP (Low-Power Plus) process technology.
As we’ve previously discussed on Rambus Press, our 56G SerDes PHY supports PAM-4 and NRZ signaling and data rates from 9.95Gbps to 58Gbps across copper and backplane channels with more than 35dB insertion loss. At the heart of the SerDes architecture is an ADC (analog to digital converter) operating at 28 GS/s that allows for adjustable power consumption and improved performance while providing low BER (Bit Error Rate) for enterprise class reliability.
Related Blogs
- I3C IP: Enabling Efficient Communication and Sensor Integration
- Exploring the XSPI PHY: Technical Characteristics, Architectural Challenges, and Arasan Chip Systems' Solution
- Setting the Pace with PCIe® Gen 7: Alphawave Semi's Success at PCIe® Devcon 2024
- Extending Arm Total Design Ecosystem to Accelerate Infrastructure Innovation
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops