Aeonic Generate Digital PLL for multi-instance, core logic clocking
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Clocking Architectures in PCI ExpressTruechip Blog - Truechip Verification TeamSep. 12, 2017 |
The PCI Express bus, originally designed for desktop personal computers, is a high-speed serial replacement of the older PCI/PCI-X bus. It is used across a range of applications, including storage devices, networking, communications, cluster interconnect etc. PCI Express is based on point-to-point topology which means separate serial links connect every device to the root complex.
PCI Express protocol provide a flexible solution for data transfers as it can be used as a data interface to flash memory devices, such as memory cards and solid-state drives. Among various advantages of PCIe, it’s scalable bandwidth and flexible clocking tops the list. Here, we will discuss about multiple clocking architectures provided by PCIe along with their advantages and disadvantages.
Clocking Architectures in PCIe
PCIe supports three kinds of clocking as stated below:
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