55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
Industry Expert Blogs
Cadence IP Is Great for AutomotiveCadence IP Blog - Paula Jones, CadenceSep. 13, 2017 |
If you’re designing chips for in-vehicle infotainment, in-cabin electronics, vision systems, digital noise reduction, and advanced driver assistance systems (ADAS), look at Cadence for the key IP to speed your design effort.
We just announced that we have collaborated with a major foundry to produce an IP portfolio that’s ASIL-B ready and ASIL-C/D capable. See the press release for full details. Cadence IP is area- and power-optimized for the AEC-Q100 Grade 2 temperature range, eliminating the need to carry Grade 1 power and area penalties into cost-sensitive automotive SoC designs.
Related Blogs
- Extending Arm Total Design Ecosystem to Accelerate Infrastructure Innovation
- Obsolete & EOL Parts
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- Moortec "Let's Talk PVT Monitoring" Series with CTO Oliver King
- Let's Talk PVT Monitoring: Thermal Issues Associated with Modern SoCs - How Hot is Hot?