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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
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Chip Dis-integrationCadence IP Blog - Tom Wong, CadenceJun. 28, 2018 |
I was asked the following question recently.
No longer are we seeing increasing amounts of functionality being crammed into chips, except under very special circumstances. Chips today are trending towards the leaner side. Is this only when power is a primary concern? Does this apply to all technology nodes or only to larger ones? What about pins – I/O has often been the limiter. What impact will this have on IP? Will this derail any notion of chip lets? Does it impact EDA tools?
So here are my observations and opinions.
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