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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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Our 56Gbps PAM4 SerDes IP Hits the LabeSilicon Blog - Tim Horel, eSiliconAug. 07, 2018 |
At eSilicon we’ve been talking about adding a 56G PAM4 SerDes to our N7 ASIC IP platform now for some time. I’m happy to say our 7nm FinFET 30 Gbaud/s PMA test chip silicon is now in the lab and we have lots of good news to share!
We’ve successfully passed the smoke test (none escaped – all good!) and are romping through the full set of registers.
All of the sub blocks have now been brought up operationally and are fully functional with their performance data showing all parameters are inside the pre-silicon modeling and calibration bounds. Detailed characterization of each is now under way.
On the speed front, both the Tx and Rx circuitries have been shown to operate over the full frequency range targeted by the design.
Power consumption of the silicon as compared to models is always a concern. Here we have been able to show it is as low as had been predicted.
