Industry Expert Blogs

During the 2018 TSMC Technology Symposium USA event, Arm’s Physical Design Group introduced its development plans for the Artisan physical IP portfolio on TSMC’s 22nm ultra-low power (ULP) and ultra-low leakage (ULL) process platforms. With an aggressive development schedule and a broad range of IPs, our enthusiasm for accelerating SoC designs has resulted in early access for our mutual customers to explore what the Artisan products and the TSMC 22nm process technologies can achieve for their complex SoC designs.

The initial announcement of the Artisan physical IP for TSMC 22nm ULL and ULP platforms included a key component - a dozen foundry sponsored memory compilers spanning the two TSMC 22nm process nodes. In addition, Arm’s own Artisan standard cell and general purpose I/O (GPIO) libraries are available for these 22nm platforms. Our teams have worked intensively to expedite the library deliverables, which means our customers can start their design evaluations now. Several of our lead silicon partners have already benefited from this close collaboration between Arm and TSMC, and are on their way towards taping out their first ultra-low power SoCs. We will share more exciting updates at Arm TechCon on October 16-18. Come join us!

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