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DSC has enabled the use of high resolution displays in televisions, PC monitors, mobiles, and automotive infotainment systems. It provides a high quality, low latency algorithm to resolve the bottleneck of high bandwidth requirements needed to support the high resolution.

In our previous blog post, 10K Resolution at 120Hz Display: A Reality Today with DSC 1.2 in HDMI 2.1, we presented how VESA (Video Electronics Standards Association) Display Stream Compression(DSC) embraced HDMI 2.1 to achieve 10K resolutions at 120Hz. In it, we also covered the basic principle of DSC with the help of a diagram which involves dividing the entire frame into slices, replacing a video line with a line of chunks, replacing Hactive (uncompressed pixels) with HCactive (compressed tri-bytes) and replacing Hblank (blanking pixels) with HCblank (blanking tri-bytes). We also mention that HCactive is much smaller than Hactive, which results in compression.

In this blog, we will showcase how exactly a frame is divided into slices, how the chunks are formed, and how the DSC model outputs HCactive bytes.

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