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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
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They Said It Couldn't Be Done! (PCIe 5.0)Express Yourself - Richard Solomon, SynopsysNov. 29, 2018 |
No, no, “it” does NOT refer to “get Richard back on the blog after some 4 months of silence” – although I think Scott was starting to think that and was probably considering threats of bodily harm!
I know there was a LOT of (very well justified, I have to confess) skepticism when the PCI-SIG announced PCIe 5.0 back in June of 2017 and claimed the spec would be “completed in 2019”. Scott talked about this a little while after that year’s Developers Conference and noted that Synopsys had already demonstrated PCIe 5.0 running 32GT/s in simulation.
One of my excuses for not blogging much lately is the raft of PCI-SIG Developers Conferences – the most recent one being in Taiwan. Here you can see me showing off the Synopsys PCIe 4.0 complete system with what we call “RAS-DES” and which I covered in my “PCIe Designs for Automotive Applications” presentation.
