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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
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HBM2 gets an upgrade as semiconductor industry eyes HBM3Rambus BlogFeb. 25, 2019 |
JEDEC recently updated its JESD235 High Bandwidth Memory (HBM) DRAM standard. As we’ve previously discussed on Rambus Press, HBM DRAM supports a wide range of use cases and verticals including graphics (GPUs), high performance computing (HPC), servers, networking and client applications. Indeed, HBM is particularly suitable for hardware that demands peak bandwidth, bandwidth per watt and capacity per area.
Densities up to 24GB, speeds hit 307 GB/s
According to JEDEC, the updated HBM standard leverages wide I/O and TSV technologies to support densities up to 24 GB per device – at speeds up to 307 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack. In practical terms, this means the standard can support 2-high, 4-high, 8-high, and 12-high TSV stacks of DRAM at full bandwidth, thereby enabling system flexibility for capacity requirements from 1 GB – 24 GB per stack
