Industry Expert Blogs

Ah it’s been a long time coming, but as many of you know, last week’s PCI-SIG Compliance Workshop #110 was the first official testing for PCI Express 4.0 compliance testing. I’m super-excited to be able to say that Synopsys had *BOTH* Endpoint and Root Complex devices pass the testing with our 16GT/s PHY IP in several different silicon processes! (Ok, ok, you can probably already guess that some of those PHYs are capable of even higher speeds, but since we’re talking just about PCIe 4.0 compliance today I won’t go into that…) Within the next few weeks, you’ll finally be able to see “PCIe 4.0 Compliant” devices on the PCI-SIG Integrator’s List, and there will be a goodly number of Synopsys entries!

It’s been a long road getting the PCI-SIG 4.0 compliance program running, and there’s been a LOT of hard work put in by Synopsys engineers behind the scenes. I’ve mentioned before how the Synopsys PCIe 4.0 Root Complex was used to develop the lane margining tool, and we’ve had both that and our PCIe 4.0 Endpoint at *EVERY* FYI and pre-FYI compliance event the PCI-SIG has held. Obviously that benefits our customers, but I’m quite proud of how much Synopsys has stepped up from an industry perspective too. Even when we didn’t have anything new to test, management didn’t hesitate to put equipment and people on the road for yet another week of compliance testing, over and over again over the last couple of years. That was a BIG help for the development of the compliance program, and several times our engineers made special trips out to visit various companies doing test program development to help debug the tests themselves.

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