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400G ultra low latency 56/112G FEC and SERDES IP sub 10ns latency
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Part 1: Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-VSifive Blog - Shubu Mukherjee, Chief SoC Architect, SiFiveJan. 14, 2020 |
This is the first in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). A DSA provides higher performance per watt than a general-purpose processor by optimizing the specialized function it implements. Examples of DSAs include compression/decompression units, random number generators and network packet processors. A DSA is typically connected to the core complex using a standard IO interconnect, such as an AXI bus.
Related Blogs
- Fast Access to Accelerators: Enabling Optimized Data Transfer with RISC-V
- Part 3: High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V
- High-Bandwidth Accelerator Access to Memory: Enabling Optimized Data Transfers with RISC-V
- High-Bandwidth Core Access to Accelerators: Enabling Optimized Data Transfers with RISC-V
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets