MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
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A painless upgrade to 22nm - the right cost with the available IParm Blogs - Claudia Pike, ArmAug. 31, 2020 |
Does your ASIC design require the lowest leakage and smallest area possible? Do you want to adopt the FinFET technology but are concerned about the expensive wafer cost? The TSMC 22nm process offers a compelling option. We are seeing many Arm partners who have used processes in 28nm, 40nm, and above, now migrating to 22nm to achieve lower leakage and a smaller area to maintain or even boost the desired performance.
The TSMC 22nm technology was developed based on TSMC’s industry-leading 28nm process, a preferred foundry solution for many different market segments in terms of its performance, power, and area scaling. However, some IC designers are looking for an economical way to meet the requirements for performance boost and lower supply voltage in applications such as digital TVs, set-up boxes, smartphones, and consumer products. For such IC designs, TSMC 22nm is the best way to increase performance and reduce power cost-effectively, which provides significant area reduction, speed gain, and power reduction compared to 28nm process.