Industry Expert Blogs
Reducing CXL Latency with PLDA and AnalogXPLDA Blog - PLDAJun. 07, 2021 |
Certain applications and hardware types -- emerging memory, artificial intelligence/machine learning, and cloud servers, to name a few -- can realize significant performance advantages when a low latency interface is employed. The CXL (Compute Express Link™) standard was developed specifically as a low latency offshoot of the ever-popular PCIeTM (PCI ExpressTM), and is finding its footing in many of the applications listed.
Let’s compare typical latency of existing standards first. Data shown below is gathered from a variety of industry sources:
From the chart, it's obvious why CXL is the high speed interface of choice for low latency applications. However, PLDA recognizes that there are applications in which CXL 2.0 latency remains a performance-limiting factor, even with CXL having the lowest latency amongst its contemporaries. Improving latency creates an opportunity for more optimized implementations for our customers, generally without cost or power implications in end systems.
Related Blogs
- Digitizing Data Using Optical Character Recognition (OCR)
- Arm and Arteris Drive Innovation in Automotive SoCs
- Why, How and What of Custom SoCs
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions