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Looking for a way to reduce effort defining and tracking functional verification goals in your Memory Controller/PHY and Subsystem Verification Project?

If you have not already deployed best practices of using Verification Plans, Functional and Timing Coverage Models in your Memory projects, learn why it is recommended…

Key Attributes of Functional and Timing Coverage Closure Flow

• Automated coverage report generation with the flexibility to specify the types different types of coverage to be enabled
• Automatic back annotation of coverage data into test plan, identifying progress against coverage goals
• Rapid identification of remaining coverage points linked to unencrypted source code, enabling faster coverage closure
• Users can extend the built-in coverage to add their own bins based on built-in VIP sampling events and groups or create their own groups with any sampling event or data
• Simulator based coverage utilities like the exclusion of bins/coverpoints/covergroups can be leveraged for the scenarios/settings not supported by IP/Subsystem

Synopsys Memory Models (VIP) have built-in verification plans, functional and timing coverage models to accelerate coverage closure. The coverage models are provided to help run complete verification scenarios across multiple combinations of configuration settings, mode register settings, features, and timing parameters.

Synopsys Memory VIP supports the latest ratified and draft specifications from standards organizations such as JEDEC, ONFi, SD, and SPI (DDR5, LPDDR5, DFI 5.0, HBM3, GDDR6, and NVDIMM-P/N) and native integrations and optimizations with VCS and Verdi.

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