Industry Expert Blogs

Many product designs are a series of compromises. Take for example, electric vehicles, wouldn’t it be great to have a 1000-mile or 1600-kilometer range in an EV? But consider what compromises would need to be made to achieve this goal. The battery would be massive and heavy, leading to an overall decrease in efficiency as you haul around the extra weight, which also affects acceleration and handling. Such a car would also be extremely expensive because of the massive battery pack. A reasonable compromise would be to have a smaller battery pack and focus on aerodynamic and motor efficiencies to maximize range but also focus on rapid charging to minimize any inconveniences.

In the chip world, all products are a series of choices and compromises, designed with a careful balance of performance, power efficiency and size (cost). One of the most basic choices for a product designer is the choice of which semiconductor process technology to use. Does a designer choose a high-performance technology at a higher supply voltage for maximum frequency and performance? This performance bias would also create a larger die area, consume a lot more power and generate more heat. Does a designer choose a more balanced technology that can be smaller in size, consume less power but will not be able to hit the highest frequencies? Or do they select a technology that focuses on the best power efficiency and the lowest leakage? Chip designers had to make these tough choices prior to the arrival of TSMC’s N3 technology.

TSMC is pleased to introduce FINFLEX for N3 at our 2022 Symposium. TSMC FINFLEX™ extends the product performance, power efficiency and density envelope of the 3nm family of semiconductor technologies by allowing chip designers to choose the best option for each of the key functional blocks on the same die using the same design toolset.

Click here to read more ...