Industry Expert Blogs

As Synopsys and TSMC collaborate to deliver high-quality IP on TSMC’s advanced FinFET processes, Synopsys announces a successful tape-out of the Universal Chiplet Interconnect Express™ (UCIe™) PHY IP on the TSMC N3E process. UCIe IP is a key element of multi-die systems, enabling designers to achieve secure and robust die-to-die connectivity in a package while delivering high bandwidth, low power, and low latency.

“TSMC works closely with Synopsys to drive semiconductor advancements that pave the way to sophisticated new electronic products for a wide range of applications,” said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. “The tapeout of the Synopsys UCIe PHY IP on our most advanced N3E process is the latest milestone in our longstanding collaboration, helping design teams realize the key benefits of multi-die systems. The development of the UCIe PHY IP in TSMC’s N3E process supports 3D IC designs that use the TSMC 3DFabric™, our comprehensive family of 3D silicon stacking and advanced packaging technologies.”

“As multi-die systems move into the mainstream of the semiconductor world, UCIe technology will play an integral role in their success,” said Dr. Debendra Das Sharma, chairman at the UCIe Consortium, which oversees the standard’s development and evolution. “We’re excited to see our members develop solutions that will help drive adoption of the standard and create a robust die-to-die connectivity solution.”

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