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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
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Synopsys and Powerchip Deliver New Advanced 3DIC Packaging Solution for AI ApplicationsSynopsys Blog - Kenneth Larsen, Director of Product Management, Synopsys, and S.Z. Chang, VP and CTO, Powerchip Semiconductor Manufacturing CorporationApr. 27, 2023 |
3DIC design is becoming a big deal. The increasing demands of AI-enabled applications in today’s market and the slowing pace of Moore’s Law have necessitated chip designers to look for other types of chip architecture that will help support the advancements that consumers and leading service providers have come to expect. Instead of simply connecting multiple silicon dies next to each other, 3DIC design offers orders of magnitude better performance, power benefits, and a smaller footprint via vertical stacking of silicon wafers or dies.
That is why Synopsys and Powerchip Semiconductor Manufacturing Corporation (PSMC) have worked together to offer a new wafer-on-wafer (WoW) and Chip-on-Wafer (CoW) solution, a specific kind of 3DIC design, by utilizing Synopsys 3DIC Compiler Platform and PSMC’s advanced process technologies to create a new joint solution that makes it possible to create circuits that stack and bond DRAM memory directly on top of a silicon chip at a reduced effort.
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