Industry Expert Blogs

At advanced nodes, in particular, there are greater process, voltage, and temperature (PVT) challenges to overcome when developing complex chips, whether they are monolithic SoCs or multi-die systems. In-chip PVT monitors have become essential “eyes and ears” in these chips, helping to enhance performance and reliability.

Synopsys has been at the forefront of chip monitoring solutions, which are part of the Synopsys Silicon Lifecycle Management (SLM) Family. Recently, Synopsys achieved successful tape-out of a PVT Monitor IP test chip on the TSMC N5 and N3E processes, marking a milestone benefiting mutual customers who are ready to design on these advanced nodes. The TSMC N3E process extends the foundry’s 3nm family with enhanced power, performance, and yield, making it ideal for compute-intensive workloads common in applications such as AI, high-performance computing, and mobile. The TSMC N5 process is based on FinFET technology, delivering roughly 20% faster speed and 40% lower power than its N7 process.

Adopted by more than 140 customers around the world, Synopsys SLM PVT Monitor IP has achieved more than 600 design-ins and is available for 28nm down to 3nm. The nature of IP is that it can be sensitive to process and manufacturing technologies, so achieving silicon-proven performance is an important part of establishing trust with chipmakers. Proven IP can save design cycles and costs. Read on to learn more about how monitoring IP can enhance chip outcomes.

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