2.5D Multi-Core Raster & Vector Graphics Processor for low-power SoCs with Microcontroller
Industry Expert Blogs
How CXL Is Improving Latency in High-Performance ComputingSynopsys Blog - Gary Ruggles , Richard Solomon , Varun Agrawal (Synopsys)Jul. 31, 2023 |
From the dawn of civilization through 2003, roughly five exabytes of data were created in total, according Eric Schmidt, past CEO of Google. By 2025, global data creation is expected to reach 180 zettabytes. This means that within the span of a single generation, we've created roughly 36,000 times the amount of data ever created—that's a lot of data! To accommodate this data explosion, the installed base of storage capacity is expected to increase at 19.2% CAGR through 2025, and the data center accelerator market is expected to grow by 25% CAGR through 2028.
It doesn't stop there.
Managing data—created, copied, stored, consumed, and otherwise proliferated from the data center to the edge—creates unique challenges for SoC designers. This includes mounting pressure to move the data through systems faster and with greater efficiency and security: Lower power. Smaller area. Lower latency. And with data confidentiality and integrity. It's essential for the interconnects in multi-die systems to have low latency along with enough flexibility to manage a variety of bandwidths and throughput. Complying with the right industry standards can help ensure design success.
Related Blogs
- How the CXL Standard Improves Latency in High-Performance Computing
- Ecosystem Collaboration Drives New AMBA Specification for Chiplets
- Intel Embraces the RISC-V Ecosystem: Implications as the Other Shoe Drops
- POWER FIRST - "Subduing The Power Management Storm"
- Mitigating Side-Channel Attacks In Post Quantum Cryptography (PQC) With Secure-IC Solutions