2.5D Multi-Core Raster & Vector Graphics Processor for low-power SoCs with Microcontroller
Industry Expert Blogs
RISC-V Summit US 2023: CHERI in full bloom!Codasip Blog - Lauranne Choquin, CodasipNov. 10, 2023 |
RISC-V Summit US 2023 did not disappoint. With more than 1,000 attendees over 3 days, our team was full on. After announcing our 700 family and the first ever commercial implementation of CHERI a couple of weeks before the event, we were prepared for what was, we believe, the best RISC-V event we’ve ever attended. From keynotes to tech talks, 101 sessions, demos, and activities at our booth, there is no doubt. RISC-V is inevitable, RISC-V is everywhere, but most importantly, RISC-V is here. We highlighted 3 themes that make RISC-V a reality: customization, automation, and security.
Customization is the way to go
Customization is our thing at Codasip, and it is fantastic to see such a growing interest in customization capabilities. On Tuesday morning the keynote by Meta highlighted the potential of RISC-V, insisting on how the standard considered custom extensions from its inception. The degrees of optimization provided vary from one RISC-V IP vendor to another – it was good to see Codasip mentioned as the company providing most design freedom to our customers thanks to our unique CodAL + Codasip Studio technology – and this is an important factor to understand. Our very own Mike Eftimakis recently wrote a blog on this specific topic. There is no one-size-fits-all approach to processor optimization. From configuration to full customization, Mike explained the different benefits and use cases and how to combine all three of them to achieve specific PPA goals.