55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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Connected by Arteris: Watching The Next Big Semiconductor Transition UnfoldArteris Connected Blog - Frank SchirrmeisterFeb. 15, 2024 |
Impressions from the 2nd Annual Chiplet Summit
From February 6th to 8th, 2024, a fascinating mix of engineers descended on the Santa Clara convention center for the Chiplet Summit. It felt like representatives from all aspects of the semiconductor ecosystem attended – providers of Semiconductor Intellectual Property (IP) like us, Electronic Design Automation (EDA) tool vendors, Wafer Fab Equipment (WFE) providers, Semiconductor Foundries, “Fabless” chip companies, and Integrated Design Manufacturers (IDMs) all in one place to discuss one thing – chiplets. The agenda varied from sessions discussing how to develop them, the architectures to integrate them, the substrates to assemble them on, the standards needed to connect them, the business models to enable them, and the industries and application domains setting requirements for them.
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