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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
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USB4 Version 2.0 - Low Power with Gen4 LinkCadence Blog - Neelabh Krishnan, CadenceApr. 30, 2024 |
USB4 Version 2.0 specification was released by the USB Promoter Group two years back. This specification enables up to 80 Gbps link speed per direction in symmetric mode and 120 Gbps link speed in asymmetric mode.
Here, we take an overview of the low power entry and exit flows in Gen4 link speed and how they have been simplified as compared to that in Gen2/Gen3 link speed.
In Gen4, the low power entry has been made uni-directional, which means that there is no need for an ACK handshake anymore, hence removing any dependency on the link partner. The low power can be symmetric (CL1 or CL2) or asymmetric (CL0s). Only CL_OFF Ordered Sets are used to enter a low power state (CL0s, CL1, CL2). Now, CL1 and CL2 can be entered only from CL0s.
