Industry Expert Blogs

The market is experiencing a major shift to the RISC-V ISA and MIPS is helping to fuel this transition with high performance RISC-V cores, including debug, trace and performance tools enabling the tools ecosystem. The commercial success of the MIPS architecture can, to some degree, be attributed to deploying advanced debug, trace and performance monitoring tools.

As the chair of the RISC-V International N-Trace TG for the past four years, let me share an important milestone in RISC-V debug, trace and performance monitoring territory. The goal of the RISC-V International N-Trace TG was to utilize the widely used and well documented IEEE-ISTO 5001 Nexus Trace Standard as the basis for an equivalent solution targeting the RISC-V architecture.

There are three fundamental RISC-V Trace specifications:

• RISC-V N-Trace (Nexus based Trace) Specification
• RISC-V Trace Control Interface Specification
• RISC-V Trace Connectors Specification

These went through a lot of scrutiny and are currently declared Frozen and in the Public Review phase with a realistic ambition to become officially Ratified ahead of the upcoming RISC-V Summit North America in October 2024.

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