Industry Expert Blogs

In today’s evolving AI/ML and HPC/datacenter landscapes, die-to-die connectivity is essential for achieving high-performance and efficient data transfer. Cadence has achieved a significant milestone with the successful tapeout of its 32G UCIe standard package IP subsystem on TSMC’s 3nm (N3P) process technology. Designed to advance the performance, power efficiency, and integration of die-to-die connectivity, the subsystem features a comprehensive range of advanced capabilities, setting a new standard in ultra-fast, high-performance interconnect solutions. Building on seven years of expertise in die-to-die solutions and the success of our proprietary 16Gbps UCIe IP subsystem, this next-generation product delivers improved performance and flexibility while maintaining the reliability and precision proven by its predecessors. Like its 16G predecessor test vehicles, the entire subsystem is implemented in silicon with the ability to transfer data off-chip through high-speed I/Os. This setup enables a user to send real traffic using their SoC prototyped in FPGA and connect to our test board to develop and confirm the full software stack.

What’s New in Our Innovative 32G UCIe Solution?

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