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Embedding FPGA technology into an ASIC or SoC has become popular for a wide variety of applications and markets, including those related to critical infrastructure, security, and defense. Engineers choose to integrate eFPGA IP into their SoCs for a number of reasons, including:

• Post-manufacturing design flexibility
• Reduced design risk
• Future proofing
• Customizable security and/or hardware acceleration
• Ability to quickly address adjacent applications and markets

Once someone has decided to move forward with an embedded FPGA design, they have a few decisions to make. One of the most important is whether to choose soft IP or hard IP.
The Soft IP approach has the advantage of slightly greater flexibility, as its parameters can be adjusted at the HDL level, then relatively easily integrated with the rest of the front-end design. However, the significant difficulty lies in the back-end design phase. FPGAs are homogeneous structures that need to be coupled tightly with the user place & route tool, to accurately represent the final user design that will go into the FPGA.

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