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The Convergence of Functional with Safety, Security and PPA VerificationSemiWiki - Nicky KhodadadNov. 25, 2024 |
Formal For All!
“Do I need a PhD to use formal verification?”
“Can formal methods really scale?”
“Is it too difficult to write formal properties that actually prove something?”
“If I can’t get a proof, should I just hope for the best?”
“Do formal methods even offer useful coverage metrics?”
…
Discouraging words to say the least, but we don’t have to live in the shadows they create anymore!
AI technologies are getting adopted faster than ever and the implementation of AI algorithms are no longer limited to purely software. In fact, breakthroughs in AI performance and the need to reduce energy consumption footprint are driving crazy innovations in hardware designs. So, for the first time, power, performance and area (PPA) along with functional verification has become a mainstream challenge; not to mention that with the adoption of AI hardware in embedded, IoT and edge – safety & security is now even a bigger challenge!
In a recent keynote at DVCon India given by Dr. Ashish Darbari, founder & CEO of Axiomise, he described how 1030 simulation cycles are not finding the bugs causing expensive respins. The respins are estimated to be 76% for ASICS with 84% of FPGA designs going through non-trivial bug escapes – the data coming from the well-known Wilson Research survey, 2022.
