Industry Expert Blogs

Although multi-die designs — an increasingly popular approach for integrating heterogeneous and homogenous dies into a single package — help resolve problems related to chip manufacturing and yield, they introduce a host of complexities and variables that must be addressed. In particular, designers must work diligently to ensure the health and reliability of their multi-die chip throughout its lifecycle. This includes testing and analysis of not only each individual die, but also die-to-die connectivity and the entire multi-die package.

Synopsys is at the forefront of multi-die design innovation, and we recently worked with TSMC to demonstrate two dies communicating via the high-speed UCIe (Universal Chiplet Interconnect Express) specification. Synopsys Monitoring, Test & Repair (MTR) IP was central to the demonstration, showing manufacturing and in-field health of the multi-die interconnect.

Read on as we explore the unique challenges of ensuring multi-die quality and reliability, why a comprehensive monitoring, test, and repair solution is crucial for chip designers, and what Synopsys and TSMC are doing to help.

Table of Contents

• The need for interconnect monitoring, test, and repair
• Comprehensive IP for multi-die health and reliability
• Demonstrating UCIe-based advances
• Our commitment to multi-die health and reliability

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