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As we enter 2025, I am pleased to announce PCIe 7.0 specification, version 0.7 is now available for member review. This specification version incorporates all the feedback we received from members on version 0.5 released in April 2024 and brings us one step closer to the full release of the PCIe 7.0 specification, targeted for 2025.

I would like to recognize the hard work of our PCI-SIG® technical work groups, composed of volunteers who generously dedicate their time to the development of the PCIe specifications. Thanks to them we are going to achieve our cadence of releasing a new specification every three years.

The PCIe 7.0 specification includes the following feature goals:

• Doubling the bandwidth of PCIe 6.0 specification (64 GT/s) to 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration
• Utilizing PAM4 (Pulse Amplitude Modulation with 4 levels) signaling
• Focusing on the channel parameters and reach
• Continuing to deliver low-latency and high-reliability targets
• Improving power efficiency
• Maintaining backwards compatibility with all previous generations of PCIe technology

PCIe 7.0 technology is a high-bandwidth, low-latency I/O interconnect targeted to support data-intensive, emerging applications, including 800G Ethernet, AI/ML, Cloud and Quantum Computing, Hyperscale Data Centers, High-Performance Computing (HPC) and Military/Aerospace.

Explore PCIe 7.0 Specification Resources

For more information on the PCIe 7.0 specification, view the following resources:

• Press Release
• FAQ
• Doubling Bandwidth Graphic and Speeds and Feeds Graphic

PCI-SIG members can review the PCIe 7.0 specification, version 0.7 in the Review Zone. Not a member? Become a member of PCI-SIG today.