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The JESD204 Standard has undergone several iterations since its initial release in April 2006, the Serdes capabilities and required encodings have been improving and adapting along the way. With the release of JESD204C and later JESD204D standards the Transmitter and Receiver no longer share a synchronization pin used for synchronization handshaking as in the previous standards. While moving away from the 8b10b encoding scheme a new method for synchronization has been proposed, in which the receiver monitors the incoming bit stream for bit patterns and determines the proper bit alignment to decode data blocks.

The Receiver (RX) will observe the data stream with the purpose of aligning with data block boundaries. In JESD204C this will be based on the 64b66b encoding’s extra two bits which hold either 01 or 10 value. The rest of the data being scrambled combinations of 11 and 00 will appear over time in all other positions so in the process of elimination the 66-bit word boundary can be observed. Following this, the additional 2 bits of the 64b66b encoding carry a sideband channel of CRC3, CRC12, FC-FEC or Command Data, as well as a pilot sequence and end of Extended Multiblock indication allowing the receiver to determine the Multiblock and Extended Multiblock boundaries. In JESD204D a similar concept is used with a pilot signal and Alignment block detection based on a grouping of Sync Header bits containing Alignment markers prepended to RS-FEC Code Words.

The Transmitter will establish its Local Clock reference (LEMC or LAC) arbitrarily or based on SYSREF or MULTIREF reference inputs, and based on the reference will start framing and sending the data. In the case of JESD204C and JESD204D, it is doing so without any knowledge of the state of the receiver. It frames up and transmits the data as it comes. As the receiver is self-synchronizing there is no need for the transmitter to take its state into account.

This scheme poses several challenges. Firstly when using a single shot type SYSREF or MULTIREF signal for aligning multiple components in the system to a common reference it is necessary to ensure all are up and running and can receive and properly detect this incoming signal. This has to be handled by upper layers outside of the protocol. This can be overcome by using periodic-type reference signals.

Another aspect often comes as a surprise to users familiar with previous versions of the standard that is the lack of first data in first data out type of transmission. The first data going into the TX no longer will be available as the first data output from the RX as was the case in previous versions of the standard. The receiver while self-synchronizing will discard several Extended Multi Blocks or Alignment Blocks while searching for the Framing and Block boundaries. Similarly, the Receiver does not have to be enabled when the Transmitter starts and in such a case it will also not receive the data being sent.

It is in this case relevant to look at the larger framing structures in JESD204 in order to group data samples logically. If needed the EMB or AB duration can be controlled by the E and A configuration parameters of JESD204C and JESD204D respectively. Hopefully allowing the Framing structure to encompass any logical grouping of data samples beyond the basic JESD204 Frame. These larger framing structures always encompass an integer number of frames and if your logical grouping of converter samples encompasses multiple frames as well it should be possible to find a common multiple such that these 2 would align. Allowing the concept of logical grouping of frames to always be aligned with the first data out of the receiver, once the receiver starts outputting data.

Chip Interfaces’ JESD204C IP Core is an established, highly optimized, fully featured, silicon agnostic for ASIC and FPGA, interoperability tested and silicon-proven implementation of the JEDEC JESD204C.1 standard. To learn more about our JESD204 C IP and how we can enable your project, please contact sales@chipinterfaces.com.