Industry Expert Blogs

Delivering optimal user experiences, including high-quality video transfer, newer laptops such as the latest AI PCs, and other leading-edge devices, requires 5nm-and-below advanced node SoCs to achieve the best power, performance, and area (PPA). However, as technology moves into sub-5nm process nodes, SoC providers face challenges such as balancing efficient power consumption with the need for lower operational voltages, often below 1.2V. Meanwhile, increasing demands for high-resolution cameras, faster frame rates, and AI-driven computing call for interfaces with higher data rates and reduced electromagnetic interference (EMI).

As these performance requirements grow more complex, innovative solutions are needed to bridge the gap between power efficiency and advanced functionality. Cadence's industry-first eUSB2V2 IP, built on the advanced TSMC N3P process and compliant with the latest embedded USB2 Version 2 standard, transforms computing devices by delivering unprecedented capabilities for laptops, AI video devices, and advanced image signal processor (ISP) systems.

Tapeout of First Complete eUSB2V2 IP Solution with TSMC N3P

eUSB2V2, a novel USB standard released in September 2024, marks a significant technological leap in the evolution of USB interfaces for modern computing systems. Cadence is the first to tape out a comprehensive eUSB2V2 interface solution that includes both PHY IP and controller IP on the TSMC N3P process, making it perfectly suited for advanced CPUs and AI-driven applications. This solution bridges legacy USB 2.0 and modern systems, ensuring seamless compatibility.

While USB 2.0's 480Mbps data rate sufficed for older laptops, modern systems require significantly higher bandwidth to handle high-resolution cameras, AI-powered computations, and real-time data processing. eUSB2V2 scales up to 4.8Gbps, providing a tenfold increase in speed. This enables seamless transmission of 4K video, smoother augmented reality (AR) applications, and limitless potential for AI integration in consumer and enterprise devices.

"With our industry-first eUSB2V2 IP solutions with TSMC N3P technology, we're addressing the combined challenges of low-voltage operation and high data-rate requirements while simplifying system design," said Arif Khan, senior product marketing group director for protocol IP in the Silicon Solutions Group at Cadence. "This tapeout milestone underscores our commitment to delivering cutting-edge IP technologies that empower our customers to create unparalleled innovations."

Industry-Leading Features for Diverse Applications

Cadence's eUSB2V2 IP solutions deliver enhanced performance, flexibility, and energy efficiency across computing, IoT, and wireless communication industries. With features like scalable link configurations, low power consumption, and superior EMI noise reduction, these solutions enable peak performance in compact designs for applications such as AI-enabled IoT devices, 4K camera systems, and 5G wireless modules.

The advanced PHY IP on TSMC's N3P process offers asymmetrical link modes up to 4.8Gbps or symmetrical configurations from 960Mbps to 4.8Gbps, allowing designers to optimize for specific use cases. Fully compliant with eUSB2V2 and UTMI 2.0 standards, the eUSB2V2 IP supports low-power states, scalable data rates, and host or peripheral flexibility, making it ideal for cutting-edge notebooks, AI-driven video processing, and next-generation communication systems.

"This partnership exemplifies our mutual commitment to anticipating technological needs and providing leading-edge solutions that advance industry innovation," said Lluis Paris, senior director of ecosystem and alliance management division, TSMC North America. "Our ongoing collaboration with Open Innovation Technology^® (OIP) partners like Cadence ensures that the latest design solutions fully utilize the high-performance and power-efficiency advantages of our cutting-edge process technologies."

eUSB2V2 Advances USB Design

Engineers, designers, and manufacturers stand to benefit from Cadence's comprehensive IP ecosystem, gaining access to robust solutions for modern computing challenges. With higher data rates, lower operating voltages, and greater flexibility, the tapeout of Cadence's eUSB2V2 IP solution with TSMC N3P technology is not just an evolution of the USB interface but a decisive leap forward for the industry. Recognizing the value of Cadence's eUSB2V2 IP solution, a key customer and early adopter has already purchased the IP for their next-generation computing device SoC.

For more information on the eUSB2V2 PHY and Controller and how they can transform your next design, explore Cadence's solutions and highlighted feature pages: USB, eUSB2V2 PHY, and eUSB2V2 Controller.

For additional resources on these topics, please read our blogs: Introduction of High Bandwidth Embedded USB2V2 (eUSB2V2) Standard and eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview.