Jan. 19, 2023 - At the RISC-V Summit in December, there were presentations halfway between a keynote and a technical session. known as RISC-V Spotlights. These were presented to the entire group of attendees but were not blessed with the keynote title. Maybe this is like the way that when a physician in Britain becomes ...

Oct. 30, 2015 - Can agile methodologies typically used in software development bring more efficiency to chip design? For UC Berkeley Professor Borivoje Nikolic, the answer is, why not? “Twenty years ago, technology people had fun making fun of ITRS predictions,” said Nikolic during his Tuesday morning keynote talk ...

Jan. 13, 2011 - A majority (if not all) SoCs today are mixed signal. Increasingly, the analog and digital portions of the design are inseparable. It is not possible any more to decompose them into separate analog and digital functions. Nothing can be treated as a black box and handed off to the other side. The new ...

Mar. 14, 2024 - In certain parts of the world, seeing a self-driving car on the road is no longer a surprise. To adapt to new driver demands such as convenience, safety, autonomy, and electrification, the automotive industry is moving to software-defined vehicles (SDVs). These require new, more powerful electrical/electronic ...

Feb. 21, 2024 - Axiomise pioneered the adoption of formal verification in the semiconductor industry since 2017. Led by visionary CEO, Dr. Ashish Darbari, who has 63 patents in formal verification, and Neil Dunlop an industry veteran with 40 years of experience, Axiomise has helped twenty customers over the last six ...

Feb. 08, 2024 - In the ever-evolving landscape of system-on-chip (SoC) development, the intricate dance between design complexity and silicon technology advancements continues to shape the future of electronic devices. While layout-versus-schematic (LVS) checking has traditionally been considered a “solved problem,” ...

Nov. 23, 2023 - In today's ever-evolving semiconductor industry, the pursuit of low-power designs has become paramount. With the increasing demand for energy-efficient devices, the need for low-power simulation methodologies has grown exponentially. One crucial aspect of low-power simulation that often remains underestimated ...

Jul. 11, 2023 - As the automotive industry embraces advanced technologies, ensuring the safety and reliability of critical systems has become paramount. ISO 26262, an international standard for functional safety, plays a central role in achieving automotive certification. In this blog, we will explore the qualification ...

Jun. 29, 2023 - If you were building a house, you’d want a solid blueprint outlining a carefully planned layout of where every room, hallway, window, and door should be. Making changes later, while the home is under construction, would be costly and time consuming. Similar considerations apply to chip design, including ...

Nov. 21, 2022 - Given our strong history of collaboration with the U.S. government and aerospace industry, Synopsys has a deep understanding of the unique challenges for semiconductors used in this sector. Harsh operating conditions, from desert to sea to space, and sensitive end applications such as rockets, radars, ...

Sep. 05, 2022 - A self-driving car. A helicopter drone on Mars. A thermostat you can adjust from across the globe. What’ll they think of next? Science fiction writer and futurist, Arthur C. Clark, said that “any sufficiently advanced technology is indistinguishable from magic.” The thing is, it’s not magic. ...

Apr. 28, 2022 - India’s top VLSI Training Services company Maven Silicon, a RISC-V Global Training Partner, conducted an insightful discussion with the industry experts Ms. Calista Redmond, CEO, RISC-V International and Mr. Sivakumar P R, CEO, Maven Silicon, on the topic “RISC-V Open Era of Computing”. To introduce ...

Apr. 04, 2022 - I am often asked the question “When is the processor verification done?” or in other words “how do I measure the efficiency of my testbench and how can I be confident in the quality of the verification?”. There is no easy answer. There are several common indicators used in the industry such ...

Oct. 14, 2021 - We describe how side-channel attacks work and detail some of the most common attack methodologies. We also explore differential power analysis (DPA), an extremely powerful side-channel attack capable of obtaining and analyzing statistical measurements across multiple operations. In addition, we provide ...

Aug. 12, 2021 - Everything is changing in the Semiconductor Industry to keep pace with 50 years old Moore’s law, the number of transistors in a chip doubles about every two years. In this article, I am delighted to address this question ‘Where are we heading?’ and explain how the semiconductor industry is evolving ...

Mar. 23, 2021 - While our USP is in circuit and IP reuse, our ongoing engagement in technology transitions is almost as important. We’re working with all of the major names in the semiconductor industry to enable a cost-effective and high-quality transfer process. There are a number of transition scenarios. For fabless ...

Jun. 07, 2018 - Debugging the complex serial protocols is the biggest challenge verification engineers face. It’s one of the most time and effort consuming activity affecting the schedule of every project. Traditional debug methodologies use a combination of loosely connected waveforms, log files, messages, and documentation, ...

Jun. 06, 2018 - Debugging the complex serial protocols is the biggest challenge verification engineers face. It’s one of the most time and effort consuming activity affecting the schedule of every project. Traditional debug methodologies use a combination of loosely connected waveforms, log files, messages, and documentation, ...

Mar. 20, 2017 - The SoC industry depends upon the availability of validated IP. SoC designs require a huge investment, and assume the external IP that is licensed from outside parties satisfies all functional and electrical specifications. To support that requirement, IP providers typically pursue a strategy to demonstrate ...

Jun. 26, 2016 - Background This project involved DFT implementation and execution of a complex Consumer SoC. T&VS’ expertise in development of DFT methodologies for complex designs and track record of providing a wide range of DFT services from scan insertion to JTAG meant that the customer could rely on T&VS to ...

Apr. 25, 2016 - Samsung Foundry had an intimate gathering recently for 200 customers and partners that I missed, but I know several people who attended. This event was a precursor to #53DAC where Samsung has the largest foundry presence. I was able to clarify what I had heard via a phone call with Kelvin Low so here ...

Sep. 18, 2015 - Greater productivity, lower power, smaller die size and greater bandwidth await teams that adopt proven methodologies to streamline design in mature geometries. Are you dreading the day when Moore’s Law comes to a grinding halt? I’m concerned, but I’m not as fatalistic as some. Here’s why: There ...

Sep. 18, 2015 - NVM Express or the Non-Volatile Memory Host Controller Interface (its prior name was NVMHCI, now shortened to NVMe) is a host-based software interface designed to communicate with Solid State storage devices across a PCIe fabric. The current Synopsys NVMe Verification IP (VIP) is a comprehensive testing ...

Apr. 13, 2015 - UVM verification methodology & System Verilog have become the de-facto standard for IP level functional verification. At Arrow Devices we have created multiple complete and customizable verification solutions successfully using UVM Verification methodology and SystemVerilog. During this process of VIP ...

Mar. 09, 2015 - After years of innovation in verification of increasingly complex should we now turn our attention to the design process itself? Since starting in verification in the early 90’s I have witnessed the introduction of code and functional coverage, constrained random, assertions, numerous metrics, formal ...

Mar. 06, 2015 - Technical press coverage traditionally focuses on the bleeding-edge nodes because that’s where the biggest challenges are. But today, our industry sits astride two distinct paths: One, next-generation process nodes. But the second path is mature nodes, which are getting extended life thanks to exploding ...

Jan. 08, 2015 - Let's look at a variety of "Design for Verification" techniques aimed at reducing bugs and making designs easier to verify. After years of innovation in verification of increasingly complex designs, should we now turn our attention to the design process itself? Since starting in verification in the ...

Aug. 29, 2014 - As the 3-D memory market matures, it continues to incubate new application opportunities and confront new challenges. Some of the challenges faced by 3D memory adoption range from technology to cost and design. On the technology front, many of the initial challenges around the interconnect reliability ...

Jul. 28, 2014 - As Moore's Law reverses and 20, 16, and 14 nanometer processes become more expensive, SoC cost reductions must come from design innovations within more mature processes and established methodologies. The days are over when companies can expect to make a profit by introducing a so-so product at first ...

Jun. 09, 2014 - SAN FRANCISCO--Sluggish growth in the EDA industry, which has frustrated vendors for a decade, can be reversed by tapping into new budgets and application areas. That was the message from Wally Rhines, Mentor Graphics CEO, during a presentation here at the 51st Design Automation Conference. Rhines, ...

May. 28, 2014 - IP integration is central to Sonics’ on-chip network business and technology strategies. We founded our company in 1996 based on the promise of IP integration to address the increasing silicon real estate afforded by Moore’s Law. Our company name, Sonics, is an acronym for Systems On ICs. For nearly ...

Mar. 03, 2014 - BARCELONA, SPAIN—It's hard (and probably intellectually dishonest) to boil down a huge event like Mobile World Congress 2014 into a single theme, but I'll give it a shot. If you wanted to pull a single, glimmering thread through all the electronics innovation packed into the Fira Gran Via here, you ...

Jan. 28, 2014 - It wasn't too long ago—perhaps even 5 to 10 years ago—that EDA and IP cores made strange bedfellows. If you've been in the industry for a few years, you remember those days (think "star IP" for one thing). Well, times change quickly in our industry. Today, IP cores are a fundamental part of EDA ...

Nov. 28, 2013 - Carey Robertson, Mentor Graphics EETimes (11/27/2013 01:48 PM EST) All of the major foundries have announced FinFET technologies for their most advanced processes. Intel introduced this transistor at the 22 nm node, TSMC for their 16 nm process, and Samsung and Globalfoundries are introducing it for ...

Oct. 03, 2013 - There are some inescapable truths in electronics design: The more challenges we overcome, the more we want to confront new ones and topple them. Today, we know, the level of complexity for most designs is staggering. To achieve our cost and form factor design goals, we are deep into the era of mixed-signal ...

Jul. 03, 2013 - In this blog, we are going to explore an alternative to the traditional FPGA approach to creating a custom system. Configurable processors can implement many compute oriented functions FPGAs can address but with some distinct advantages. I talked to Bob Beachler, vice president of marketing, operations, ...

Dec. 17, 2012 - Today, EDA requires specialization. Elaborating on EDA over the past decade, Dr. Walden (Wally) C. Rhines, chairman and CEO, of Mentor Graphics, and vice chairman of the EDA Consortium, USA, said that PCB design has been flat despite growth in analysis, DFM and new emerging markets. Front end design ...

Nov. 02, 2012 - In this column, I'm starting a mini-series on the development of Intellectual Property (IP) cores from FPGA suppliers. The subject of IP cores from third-party vendors will be a follow-on topic since there are significant issues that differ between IP delivered from the FPGA manufacturers and third-party ...

Mar. 08, 2012 - Last week was DVCon, probably the best conference of the year for those interested in functional verification. DVCon stands for Design and Verification Conference and it used to be that it concentrated on design. That was when languages such as Verilog and VHDL were the hot issues of the day. Today, ...

Dec. 07, 2011 - At this point, everyone has reported on the merger of OSCI and Accellera, two standards groups that operate in the EDA and IP domain. The principle output from OSCI has been the SystemC language and technologies surrounding it, such as the TLM 2.0 transaction level modeling interface. Accellera has ...