"High-Level-Modeling"

• "IP integration in embedded systems modeling" by Ali Koudri, Samy Meftali & Jean-Luc Dekeyser from LIFL
  
  
• "Implementation  of  a  SystemC  Assertion  Library" by Wolfgang Ecker, Volkan Esen, Jacob Smit, Thomas Steininger & Michael Velten from Infineon Technologies
  
  
• "ESL Requirements for Configurable Processor-based Embedded System Design" by Grant Martin from Tensilica
  
  
• "A Novel Modeling and Verification Environment for Rapid IP Prototyping" by Mikhail Baklashov & Manish Bhattarai from Simantix Systems, Inc.
  
  
• "A Case Study in Rule-Based Modeling" by Wolfgang Ecker from Infineon Technologies & Volkan Esen from Infineon Technologies & Mieszko Lis from Bluespec Inc. & Thomas Steininger from Infineon Technologies
  
  
• "Cycle Accuracy Analysis and Performance Measurements of a SystemC model" by Smita Ratnam & Aniruddha Baljekar from Philips Semiconductors
  
  
• "Reusing Verilog IP Cores in SystemC Environment by V2SC" by Leila Mahmoudi Ayough, Ali Haj Abutalebi, Ali Iranmanesh & Moji Atarodi from Ascend Design Automation
  
  
• "A SystemVerilog DPI Framework for Reusable Transaction Level Testing, Debug and Analysis of SOC Designs" by Rich Edelman from Mentor Graphics

• "FAUST: On-Chip Distributed Architecture for a 4G Baseband Modem SoC" by Yves DURAND, Christian BERNARD & Didier LATTARD from CEA/LETI
  
  
• "Single Poly EEPROM on standard CMOS process" by Frederic BERNARD from SPINTRON
  
  
• "Design and Optimization of Low-Power Processor for Wireless Sensor Network" by zhao gang from VLSI & System Lab, Beijing University of Technology & Wu WuChen from VLSI & System Lab, Beijing University of Technology
  
  
• "IP CORE FOR REGULATION VOLTAGE ADJUSTMENT IN ELECTRIC ENERGY DISTRIBUTION SYSTEMS" by Manoel Firmino de Medeiros Jr., Ivan Saraiva Silva, José Alberto Nicolau de Oliveira & Max Chianca Pimentel Filho from UFRN
  
  
• "A Low Complexity Register-Exchange Viterbi Decoder for Tail-Biting Convolutional Codes" by suchang chae from ETRI
  
  
• "A Flexible, Low Power, High Performance DSP IP Core for Programmable Systems-on-Chip" by Paul Heysters, Gerard Rauwerda & Lodewijk Smit from Recore Systems
  
  
• "RtrASSoc51-Adaptable Superscalar Reconfigurable Programmable System on Chip – The Reconfigurable tools for DSR a Development System" by Jorge Silva from University of Sao Paulo

• "Risk versus Reward: Where Do Your IP Reuse Practices Fall?" by Kathy Werner from Freescale Semiconductor, Inc
  
  
• "Market-Driven Open-Cores SoC Experience" by Bohumir Uvacek from Toshiba
  
  
• "Integrating a multi-vendor ESL-to-silicon design flow using SPIRIT" by Christopher Lennard from ARM, Mark Noll from Synopsys, Chulho Shin, Chris Baxter & Peter Grun from ARM
  
  
• "How to Create Efficient IP Standards and Why You Should Care" by Dan Moritz from VirageLogic & Saverio Fazzari from Cadence
  
  
• "IP packaging and delivery based on XML signatures: Best Practice to standard" by Gabriele Saucier from Design And Reuse
  
  
• "Business Considerations in SOC IP Procurement" by Kenneth Wagner from PMC-Sierra, Inc. & Alan Nakamoto from PMC-Sierra, Inc.
  
  
• "Bridging the Gap between IP Provider and Silicon Design Center" by Ron Landry from AMI Semiconductor
  
  
• "Methodology for protection and Licensing of HDL IP" by Tarun Batra from Cadence Design Systems & Deepak Pant from Cadence Design Systems
  
  
• "Automated Implementation Flows based on IP-level constraints and synthesis intent in XML" by Denis Bussaglia from Synopsys & Marino Strik from Philips Semiconductors & Mark Noll from Synopsys & Geoff Moll from Philips Semiconductors & Ralf Gaisbauer from Philips Semiconductors

• "Computational Nano Technology and its impact on Future Electronics" by Chandrasekaran Subramaniam from St. Joseph's College of Engineering, Dinesh.C & Arun Kumar.S.B from MNM Jain Engineering College
  
  
• "On-chip di/dt Detector IP for Power Supply" by Toru Nakura, Makoto Ikeda & Kunihiro Asada from University of Tokyo
  
  
• "A High Level Power modeling IP Methodology for SoC Design Based on FPGA Approach" by david elléouet from IETR/INSA & Nathalie Julien from LESTER/UBS & Dominique Houzet from IETR/INSA
  
  
• "Towards Activity Based System Level Power Estimation" by Eike Schmidt from ChipVision Design Systems & Frank Schirrmeister from ChipVision Design Systems
  
  
• "Analog IP Reuse in Nano Technologies" by Sherif Hammouda from Mentor Graphics & Hazem Said from Ain Shams University & Mohamed Dessouky from Mentor Graphics & Mohamed Tawfik from Mentor Graphics & Quang Nguyen from On SemiConductor

• "A Strategy for Specifying SystemC Micro-controllers Models using the ADL ArchC" by Patricia Freire, Vitor Schwambach & Edna Barros from CIn- UFPE
  
  
• "A Multiplier Module Generator Based on Arithmetic Description Language" by Naofumi Homma, Yuuki Watanabe, Kazuya Ishida & Takafumi Aoki from Tohoku University & Tatsuo Higuchi from Tohoku Institute of Technology
  
  
• "Transaction Level Model of IEEE 1394 serial bus link layer controller IP core and its use in the software driver development" by Filip Rak from Evatronix S.A. & Wojciech Sakowski from Silesian University of Technology

• "Design Of Wireless Systems Utilizing Scratchpad Memories" by Goran Panic, Zoran Stamenkovic, Klaus Tittelbach-Helmrich, Jens Lehmann & Gunter Schoof from IHP Microelectronics
  
  
• "A Design for Improving the Channel Time Efficiency in Wireless Network" by Ji Eun Kim, Young Ae Jeon, Sangjae Lee & Sang Sung Choi from ETRI
  
  
• "Real-Time video system Design based on the NIOS II processor and uClinux" by Ahmed Ben Atitallah, Patrice Kadionik & Fahmi Ghozzi from ENIS, Patrice Nouel from IXL-ENSEIRB & Nouri Masmoudi from ENIS

• "Novel techniques for very high speed instruction set simulation" by Nagendra Gulur from Texas Instruments
  
  
• "Efficient creation of peripheral simulation from specifications" by Nagendra Gulur from Texas Instruments & Archana Shetty, Nisha Nair & Shilpa R from University Visvesvaria College of Engineering
  
  
• "Connecting reality and simulation: Couple high speed FPGAs with your HDL simulation" by Stefan Reichör from Gleichmann Electronics Research & Martina Zeinzinger from Gleichmann Electronics Research & Markus Pfaff from University of applied sciences, Hagenberg

• "A NoC-based communication framework for seamless IP integration in complex systems" by Fabien CLERMIDY, Didier VARREAU & Didier LATTARD from CEA/LETI
  
  
• "High Speed Connected Component Labeling as a Killer Application for Image Recognition Systems by Dynamically Reconfigurable Processor" by Noriyasu Matsuno & Mitsumasa Yoshimura from IPFlex Inc.
  
  
• "Hardware/Software Partitioning and Interface Synthesis in Networks On Chip" by Francesco Regazzoni from ALaRI, University of Lugano & Marcello Lajolo from NEC Labs America, Inc.
  
  
• "Design and FPGA Implementation of a Interpolative Neural Network for Digital Image Zooming" by Sheng - Hsien HSIEH from Department of Electrical Engineering, I-Shou University & Ching-Han CHEN from Department of Electrical Engineering, I-Shou University

• "Unique Approach to Verification of Complex SoC Designs" by Arie Komarnitzky, Nadav Ben-Ezer & Eugene Lyubinsky from Avnet ASIC
  
  
• "Verification methodology for standards-based IP & SoC" by Andy Montador from Cadence Design Systems
  
  
• "A Unified DFT Verification Methodology" by Stylianos Diamantidis, Iraklis Diamantidis & Thanasis Oikonomou from Globetech Solutions
  
  
• "Dynamic Assertion Based Verification using PSL and OVL." by Aniruddha Baljekar from Philips Semiconductors
  
  
• "New verification methodology for SoC designs" by sudha Raman from STMicroelectronics
  
  
• "Transaction-based Debug of PCI Express Embedded SoC Platforms" by Bindesh Patel from Novas Software & Sean Smith from Denali Software, Inc

• "Using dynamic run-time scheduling to improve the price-performance-power efficiency of heterogeneous multicore SoCs" by Mark Lippett from Ignios
  
  
• "Quantitative Analysis of Fractional Clock Division for Systems-on-FPGA" by Thomas Preusser, Steffen Koehler & Rainer Spallek from TU Dresden
  
  
• "Wireless Infrared Communication – Simple and Efficient Design Flow" by Frank Deicke from Fraunhofer IPMS & Hagen Graetz from Fraunhofer IPMS
  
  
• "Design Methodology of UDF and FDF FIR Filtering IP Core for reusable SoC Design" by Umar Farooq, Muhammad Saleem and Habibullah Jamal from UET Taxila

• "IDRT-aware SoC Integration Flow" by Fréderic POULLET, Christophe GAILLARD & Lucille ENGELS from Dolphin Integration
  
  
• "Enabling Rapid Adoption of the AMBA 3 AXI protocol based design with Synopsys DesignWare IP" by Mick Posner from Synopsys
  
  
• "Designing a CE-ATA Verification Environment for SoC Applications" by Ioannis Mavroidis from Globetech Solutions
  
  
• "High Quality IP creation through Efficient Packaging and Multiple Configuration Testing" by Prabuddha Mitra from Synopsys
  
  
• "The Perils of RF IP" by David Schwan from Micro Linear

• "FPGA prototyping of complex SoCs: Partitioning and Timing Closure Challenges with Solutions" by KODAVALLA VIJAY KUMAR & NITIN RAVERKAR from WIPRO TECHNOLOGIES
  
  
• "FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM" by Rick Mosher from AMI Semiconductor
  
  
• "FPGA Prototyping as a Verification Methodology" by Ron Landry & Ken Pelic from AMI Semiconductor
  
  
• "Debug IP for SoC Debug" by William Orme from ARM
  
  
• "Time to Find a Bug" by Jens Kjelsbak from IPextreme

• "Getting the vision implemented : an update on SPIRIT Consortium progress" by Chris Lennard, Vice Chair SPIRIT Consortium
  
  
• "65 nm SoC/IP Reuse design based on an emerging standard : SPIRIT" by Olivier Florent & Francois Remond, STMicroelectronics Grenoble France
  
  
• "The SPIRIT standard and SoC Design Efficiency" by Ralph von Vignau , Philips Semiconductor
  
  
• "Infineon's motivation to join SPIRIT" by Wolfgang ECKER
  
  
• "LSI Logic’s motivation to join SPIRIT" by Dr Gary Delp
  
  
• "Freescale’s motivation to join SPIRIT" by Kathy Werner
  
  
• "Enabled VLIW Processor Platform" by Victor Berman