SOC DESIGN PLATFORM

• "Soc interconnect performance verification based on hardware emulator" by Denis LEHONGRE from Stmicroelectronics
  
  
• "How a retargetable tool flow for ASIP design enables SoCs for multitudes of applications" by Gert Goossens, Dirk Lanneer, Werner Geurts & Johan Van Praet from Target Compiler Technologies
  
  
• "A Platform Based SOC Design Environment" by Jeonghun Kim from Korea Univ/Mewtel Inc
  
  

• "Comprehensive Change Management for SoC Design" by Sunita Chulani & Stanley Sutton Jr. from IBM T. J. Watson Research Center, Gray Bachelor from IBM Global Business Services & P Santhanam from IBM T. J. Watson Research Center
  
  
• "Light-weight Communication Infrastructure for IP Integration" by Jesús Barba, Fernando Rincón, Francisco Moya, Juan Carlos López , Félix Jesús Villanueva & David Villa from University of Castilla-La Mancha
  
  
• "A Next Generation IP based collaborative Station" by Mourad Hamdoun, Brahim Missaoui & Gabrièle Saucier from Design and Reuse
  
  
• "Unifying Diversity – A classic example of Reusability" by Gaurav Jalan from SiRF Technology & Sandeep Ahuja from SiRF Technology
  
  

• "STBus complex interconnect design and verification for a HDTV SoC" by Olivier CAUVET from STMicrolectronics & Francoise CASAUBIEILH from Synopsys
  
  
• "A High Performance Platform Architecture for MIPS® Processors" by Jack Browne from MIPS Technologies, Inc.
  
  
• "Using a Versatile, Independent IP Platform" by Jim Bruister from SoC Solutions & Bill Finch from CAST
  
  
• "Reusable debug infrastructure in SoC prototyping: Embedded WiFi case study" by Haridas Vilakathara from NXP Semiconductors
  
  
• "Developing a Reusable IP platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment" by Brendan Mullane & Ciaran MacNamee from CSRC, University of Limerick
  
  

• "A Security Tagging Scheme for Application Specific Intellectual Property Cores" by Carol Marsh from iSLI / Algotronix & Tom Kean from Algotronix
  
  
• "Protecting IP in a Modern Design Flow" by Dan Moritz from Virage Logic & Saverio Fazzari
  
  
• "High Performance Connectivity IP – Avoiding Pitfalls When Selecting An IP Vendor" by Navraj Nandra from Synopsys
  
  

• "An Implementation Study on Fault Tolerant LEON-3 Processor System" by Zoran Stamenkovic, Christoph Wolf & Gunter Schoof from IHP GmbH & Jiri Gaisler from Gaisler Research
  
  
• "A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect" by Mohammad Urfianto, Tsuyoshi Isshiki, Arif Khan, Dongju Li & Hiroaki Kunieda from Tokyo Institute of Technology
  
  
• "RAID6 accelerator in a PowerPC IOP SOC" by Gerard BOUDON, Haluk Aytac & John Fakiris from AMCC
  
  
• "High-resolution CMOS Rotary Encoder SoC Using Magnetic Sensor Array and Statistical Angle Calculation Circuit" by Kazuhiro Nakano & Shoji Kawahito from Shizuoka Univ. & Toru Takahashi & Yoshitaka Nagano from NTN Corp.
  
  

• "IP Core for an H.264 Decoder SoC" by Wagston Staehler from UFRGS & Altamiro Susin from UFRGS
  
  
• "Silicon IP for Programmable Baseband Processing" by Eric Tell, Anders Nilsson & Christer Svensson from Coresonic
  
  
• "1Tb/s 3W Inductive-Coupling Transceiver IP for 3D-Stacked SiP" by Noriyuki Miura from Keio University, Yoshihiro Nakagawa, Masamoto Tago & Muneo Fukaishi from NEC Corporation & Tadahiro Kuroda from Keio University
  
  
• "Hardware Implementation of a Combined Interleaver and DeInterleaver" by Shyam Shenoy, Chandrashekar B U & Sayandeep Nag from Synopsys (I) Pvt Ltd
  
  
• "IP CORE FOR RAID 6 HARDWARE ACCELERATION" by Michael Gilroy from Institute for System Level Integration & James Irvine from University of Strathclyde & Gideon Riddell from A2E Limited
  
  

• "IP-based design for analogue ASICs : a case study" by Timothée Levi, Noëlle Lewis, Jean Tomas & Pascal Fouillat from IXL laboratory
  
  
• "Fully Digital Implemented Phase Locked Loop" by Michael Gude & Gerriet Mueller from Cologne Chip AG
  
  
• "Deploying Mixed Signal IP - Is 'No Re-spin' Just Spin?" by Brendan Farley from Silicon & Software Systems Ltd (S3)
  
  
• "System Level design automation of pipelined analog-to-Digital Converters" by Mohamed Saeed from SWS & Mohamed Dessouky from Mentor Graphics
  
  
• "Fully Digital Implemented Delta-Sigma Analog to Digital Converter " by Michael Gude & Gerriet Mueller from Cologne Chip AG
  
  
• "A Unified Analog Design and Process Framework for Efficient Modeling and Synthesis" by Firas Mohamed, Yoann Courant & Stephane Bergeon from InfiniScale
  
  

• "Design and implementation of Parallel and Pipelinined Distributive Arithmetic based Discrete Wavelet Transform IP core" by Cyril Prasanna Raj P from MS Ramaiah School of Advanced Studies
  
  
• "Integrating PCI Express IP in a SoC" by Ilya Granovsky & Elchanan Perlin from IBM
  
  
• "BACK-END TOOL FLOW FOR COARSE GRAIN RECONFIGURABLE IP BLOCK RAA" by Tapio Ristimaki, Claudio Brunelli & Jari Nurmi from Tampere University Of Technology
  
  
• "Top Down SoC Floor planning with ReUse" by Fuad Abu Nofal & Monica Nofal from ChipEDA
  
  
• "MpNoC Design: Modeling and Simulation" by Simon DUQUENNOY, Sébastien LE BEUX, Philippe MARQUET, Samy MEFTALI & Jean-Luc DEKEYSER from INRIA Futurs, Lille
  
  
• "Realizing the Performance Potential of a PCI Express IP" by K Yogendhar, Vidhya Thyagarajan & Sriram Swaminathan from Rambus Chip Technologies (Pvt) Ltd.
  
  

• "High Density FPGA Package BIST Technique" by Douglas Goodman, James Hofmeister & Justin Judkins from Ridgetop Group Inc.
  
  
• "A Python based SoC Validation and Test Environment" by Nicolas Tribie & Olivier Fargant from Wipro-Newlogic
  
  
• "Remote Testing and Diagnosis of System-on-Chips using Network Management Frameworks" by Oussama Laouamri & Chouki Aktouf from DeFacTo Technologies
  
  
• "Re-Use of Unit level verification framework" by Aniruddha Baljekar from NXP Semiconductors
  
  

• "USB2 PHY Verification" by Hugo Cavalcanti & Gary Miller from Freescale Semiconductor
  
  
• "A New Methodology for Hardware Software Co-verification" by Venkata Giri Kumar, Manoj Ariyamparambath & Bashuman Deb from Synopsys (India) Pvt Ltd
  
  
• "Development of Verification Environment for Layered Protocol using SystemVerilog" by Ganesh Dekate from Infineon Technologies
  
  

• "FPGA Prototyping of Complex SoCs: RTL code migration and debug strategies" by Kodavalla Vijay Kumar & Singh Devendra Bahadur from Wipro Technologies
  
  
• "Fast Virtual Prototyping for early software design and verification" by Amit Garg from CoWare
  
  
• "Practical Applications of Data Abstraction Techniques for Embedded Systems Debug" by George Bakewell from Novas Software, Inc. & Charles Janac from Arteris
  
  
• "An Analog Verification and IP Development Environment" by Stephan Weber from Cadence  
  
  

• "Distributed software behaviour analysis through the MPSoC design flow" by Julien Bernard from INRIA/MOAIS, Serge De Paoli from STMicroelectronics & Fabrice Salpetrier from IMAG/LSR
  
  
• "Transaction Recording, Modeling and Extensions for SystemVerilog" by Rich Edelman, Mark Glasser, Chris Cotterel & Bill Cox from Mentor Graphics
  
  
• "Increasing System-on-Chip reusability using Hardware Abstraction Layer" by Raghawendra Singh from BITS Pilani
  
  

• "IP reliability and the evaluating technology" by Luo Hongwei, En Yunfei & Xiao Qingzhong from China Electronic Product Reliability and Environmental Testing Research Institute
  
  
• "Processor Design And Implementation for Real-Time Testing of Embedded Systems" by shyam Akashe from ITM & Yagendra Gupta from ITM
  
  
• "Silicon validated IP cores designed by the Brazil-IP Network" by Ana Karina Rocha from UFCG & Patricia Lira from UFPE & Yang Yun Ju from UNICAMP Elmar Melcher from UFCG & Edna Barros from UFPE
  
  
• "Smart Interconnects with Smart IP" by WARREN Savage from IPEXTREME & Jeff Haight from Sonics
  
  
• "Design and real time hardware implementation of a generic fuzzy logic controller for a transport/diffusion system" by Sukrit Shankar from Conexant Systems India Pvt. Ltd. & Jaydev Sharma from IIT Roorkee & Shamim Akhtar from JIIT, Noida & Chetana Shanta Patsa from IBM,India
  
  

• "A Heuristic Energy Aware Application Mapping algorithm for Network on Chip" by Armin Mehran from Iran Telecom Research Center/Azad University, Science & Research Campus & Ahmad Khademzadeh from Iran Telecom Research Center
  
  
• "Synthesizable Switching Logic for Network-on-Chip Designs on 90nm Technologies" by Tapani Ahonen & Jari Nurmi from Tampere University of Technology
  
  
• "GA based Intelligent Packet Routing to support QoS in MANET" by Sonal Popat from ISTAR - S.P. University & Darshan Amrutia from ISTAR - S.P. University
  
  
• "Methods of selection of structural and architectural organization of multicast switches" by Yury Sheynin & Ellin Suvorova from Saint-Petersburg University of Aerospace Instrumentation
  
  

• "XML-Based Assertion Generation" by Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger & Michael Velten from Infineon Technologies AG
  
  
• "Accelerated IP Model Development" by Bill Neifert from Carbon Design Systems
  
  
• "Design of a C library for the implementation of 3D graphics applications on a SoC" by Fabio Garzia, Claudio Brunelli, Juha Killiainen & Jari Nurmi from TUT
  
  
• "System on Chip Development. How to put into practice a Submit, Integrate, Test and Release" Methodology."" by Felix Beniamin from ENOVIA MatrixOne
  
  

• "A Unified CPU Modeling for SoC Verification" by RAVI KUMAR AVUDAI NAYAGAM from HCL Technologies Ltd.
  
  
• "Measurable Verification Methodology for Highly Configurable IP Cores" by Vishal Namshiker from Synopsys
  
  
• "Verification planning for Reusable core based designs" by Anjali Vishwanath & Ranga Kadambi from Infineon Technologies Asia Pacific Pte Ltd
  
  
• "Improving ASIC Design Verification using FPGAs and Structured ASICs" by Pat Mead from Altera
  
  

• "Transaction Level Model of the USB On-The-Go controller IP core" by Marek Podeszwa & Filip Rak from Evatronix SA & Wojciech Sakowski from Silesian University of Technology
  
  
• "IPextreme Solution" by WARREN Savage from IPEXTREME-->
  
  

• "Using IP to Accelerate the Adoption of New Automotive Standards" by Warren Savage from IPextreme
  
  
• "Open Source FlexRay Communication: Time Triggered OS" by Hiroyuki Hattori from Witz Corporation
  
  
• "FlexRay – The Hardware View" by Stefan Shmechtig from IPextreme
  
  
• "eVerification Environment for FlexRay Advanced Automotive Networks" by Stefan Schmechtig from IPextreme
  
  

• "IP encapsulation: Approach and Case Study" by Fatma Abbes from ENIS
  
  
• "A generic Spirit compliant Loose Generator interface" by Gabiele Saucier from Design And Reuse
  
  
• "IPZIP - AN IP DISTRIBUTION FRAMEWORK" by Cristiano Araujo, Edna Barros & Millena Gomes from UFPE